Frequency Swept Source using Xilinx DDS Compiler

Frequency Swept Source using Xilinx DDS compilerAbstract This newspaper presents a module which basically is a frequency swept address ( cheep sign of the zodiac), which surface areas from 1MHz to 10 MHz in 10 microseconds. The module was pictureed by using the DDS IP core in Xilinx. It is blueprinted to be ramble on the ZedBoard Zynq Evaluation and Development Kit (xc7z020clg484-1).Keywords-frequency swept source sing bode DDS CompilerThis module was designed as a plane section of the coursework assignment of ECE 580B4 FPGA Signal Proc/Software Defined Radio. The purpose of this assignment was to design a frequency swept source which will be extensively used in testing the Digital FIR filters that are to be designed and implemented as a part of the future coursework.A. DDS IP Core CompilerThe Xilinx DDS core compiler implements high performance soma generation and stagecoach to sinusoid circuits with AXI-4 stream compliant features. The core sources sinusoidal waveforms for use in many applications. This module comes with an inbuilt sine and cosine Look up table and a phase generator. For the purposes of this assignment, the DDS compiler was put together to receive a streaming phase input and the phase largeness resolution is set to 8 bits to make the design more place efficient and to make the simulations run faster.B. Frequency swept Source material bodyThe Frequency Swept source is coded as a synthesizable Verilog module. In this Verilog Module, The DDS Compiler was instantiated and appropriate phase data is streamed by feeding the data into the s_axis_phase_tdata. s_axis_phase_tvalid is unendingly set to 1 for the purposes of this assignment.The frequency swept source is expected to sweep from 1Mhz to 10 Mhz in 10 micro-seconds. This basically translates to an increment of 1Mhz in every microsecond. So, initially the increment has been calculated to generate a 1Mhz signboard and then the increment is ramped up linearly to generate the de sired chirp signal. The following expression has been used to derive the phase increment shelter.F expose = fclk* (dt)/ (2(B))Here, fout is the railroad siding frequency, fclk is the clock frequency, dt is the phase increment and B refers to the phase width. The above equation, for an 8bit phase width, 100 Mhz source to generate a 1Mhz payoff signal basically expects a phase increment of 2.56. But in this design this has been rounded off to 3. So, a phase increment of 3 refers to an output of 1Mz signal and a phase increment of 6 refers to an output of 2Mhz signal etc. The value of phase increment should realistically increment upto 25.6, so this number will be rounded off to 25. Now, is basically comes prevail over to generating 22 different values for phase increment in a matter of 10 microseconds. In out design, the timescale has been set to 1ns. Now to mannequin out the counteract to increase the value of phase increment in steps of 1, we need to impart a suitable amount o f delay. This delay is calculated as shown belowDelay = 10u/(22) * 103 nano seconds. Assuming a delay of one unit refers to one nano second.The value of delay comes out to be 454.54 cycles. So, basically, we increase the value of phase-increment in steps of 1 from a starting value of 3 after every 455 clock cycles. This makes sure as shooting we are getting appropriate ramping up of the phase increment value to generate the desired sweep. module freq_sweep( input clk, output reg 70 sin, output reg 70 cos ) reg70 phase_data wire phase_valid wire 150 nco_data wire nco_valid integer i assign phase_valid =1 initial bring forth phase_data = 3 end dds_compiler_0 DUT( .aclk(clk), .m_axis_data_tdata(nco_data), .m_axis_phase_tvalid(nco_valid), .s_axis_phase_tvalid (phase_valid), .s_axis_phase_tdata (phase_data) ) always (posedge clk) begin if (phase_valid == 1) begin sin = nco_data 158 cos = nco_data 70 end end always begin for (i=3 i